VLSI Questions

1. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
2. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram.
3. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
4. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
5. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
6. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
   Draw a 6-T SRAM Cell and explain the Read and Write operations
7. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
8. What happens if we use an Inverter instead of the Differential Sense Amplifier?
9. Draw the SRAM Write Circuitry
10. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
11. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
12. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
13. What’s the critical path in a SRAM?
14. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
15. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
16. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
17. How can you model a SRAM at RTL Level?
18. What’s the difference between Testing & Verification?
19. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)